Sample-and-hold circuits (also called sample-and-hold amplifiers, and abbreviated in the singular as an "sha") are widely used in electronic systems, particularly where it is necessary to convert an analog signal into a digital stream or into a digital word for further processing.
In many applications, it is desired that the sample-and-hold circuitry hold on its output for a considerable time the value of the sampled input signal. Frequently, the analog signal (which may be a voltage or a current but is shown in the illustrations herein as a voltage) is sampled onto a capacitor which is used to hold the sampled value or a voltage representing same. A problem exists in the use of such capacitor-based circuits, however, in that the analog voltage level stored on a holding capacitor will "droop"--i.e., steadily fall--over the hold interval, principally as a result of current leakage. Attempts have been made to minimize the impact of this droop by improving the quality of hold capacitors and by ensuring that the holding capacitors are connected to buffers specially designed to draw negligible input current. Also, the capacitance may be increased to reduce droop, but this has a negative impact on the circuit's ability to process high speed signals.
In capacitor-based sample-and-hold circuits, therefore, if the sampled value must be stored for any significant amount of time, the capacitor must be periodically recharged by highly accurate sub-circuits, to refresh the held voltage. This imposes an undesirable overhead on the circuitry and is particularly problematic in situations where a number of sample-and-hold circuits are used, requiring regular polling to refresh stored charges and possibly slowing down the overall operation.
Of particular note, it is sometimes desirable to be able to hold a series of analog sample values of an input signal, and that the held values be--and remain during a long hold period--highly accurate representations of the input at the time of sampling. Using capacitor-based circuitry requires at least one holding capacitor for each sample, in addition to the requisite refresh circuitry. Holding capacitors, however, typically are physically large elements and occupy a considerable amount of area on a die if they are fabricated monolithically with the circuitry. This limits the area available for other components and circuits and raises the cost of the product in which the sample-and-hold circuits are used. If capacitors external to the die are employed, they add substantial cost and physical size as well as introducing unwanted temperature dependencies.
To this end, there have been developed certain so-called "infinite" sample-and-hold circuits ("ISHA") wherein a digital-to-analog converter generates analog voltage which is compared with an input analog signal and a control circuit forces the generated analog voltage to equal the input analog voltage. The generated analog voltage may then be maintained by maintaining the digital code input to the DAC. However, the DAC may introduce linearity errors, making it difficult to reproduce accurately the input analog signal.
As shown in National Semiconductor's application note publication AN-294, one approach to providing an infinite sample-and-hold amplifier uses a separate ADC and DAC in combination with external circuitry. The disclosed approach, however, requires a large number of discrete components. Further, the accuracy of the system is limited by the accuracy of the two converters; to achieve greater than eight-bit accuracy requires expensive components. Additionally, offset errors in the converters and output buffer, together with gain errors, all combine to reduce the ability to accurately reproduce the input voltage at the output.
Even when the components for such an ISHA are integrated into a single chip, the overall accuracy is still limited by the converters and by the matching between the ADC and DAC.
A variation on this approach is shown in National Semiconductor's application note AN-245. There, the architecture employs a DAC, a successive approximation register (SAR) and a comparator to converge the output voltage to the input sample. However, this approach requires multiple external components and suffers due to offset errors, sample and hold droop, and other factors.
Additionally, in certain types of equipment, such as automated test equipment (ATE), it is desirable to employ digital to analog converters (DACs) to generate from digital control signals analog test signals for driving devices to be tested. In such situations, either a DAC is provided for each signal level required or, if a good sample-and-hold circuit is available, a single DAC output is demultiplexed using a (capacitor-based) sample-and-hold circuit for each level needed. The DAC approach requires accurate high resolution DACs, which are expensive, and using capacitor-based sample-and-hold circuits requires extensive refresh circuitry.